发明名称 CLOCK SUPERVISORY SYSTEM
摘要 PURPOSE:To prevent an accident attending on the operation of stopping clocks, by equipping a unit, which operates synchronizing with clock pulses, with FF performing inversion by clock pulses, a delay circuit, exclusive logic sum circuit, and supervisory circuit composed of LPF. CONSTITUTION:In the numerical controller, clock pulse (a) obtained from the output pulse of oscillator 1 by waveform-shaping 2 is divided by FF7 and division signal (b) and signal (c) obtained from signal (b) through approximately 180 deg. delay 9 are inputted to exclusive logic sum circuit 8. Output signal (d) of circuit 8 has its high-frequency component removed by LPF10 to obtaine signal (e). As a result, when pulse (a) under a constant supervision stops, alarm generating circuit 11 is operated to send out an alarm and also to turn servo system 4 OFF, thereby stopping work machine 5. The stop of clock pulses is therefore detected automatically and an accident caused by stopping pulses can be prevented.
申请公布号 JPS55951(A) 申请公布日期 1980.01.07
申请号 JP19780074343 申请日期 1978.06.20
申请人 FUJITSU FANUC LTD 发明人 FUKUYAMA TAKAOMI;ISOBE SHINICHI
分类号 G06F11/00;G05B9/02;G05B19/18;G06F1/04 主分类号 G06F11/00
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