Signal processor multiplexed pulse width modulated signals - uses limiting circuit to reduce cross-talk and non-linearity

摘要

The signal processor is designed to reduce cross-talk and non-linearity when handling pulse-width-modulated, multiplexed signals. This is achieved by limiting in which the pulse width is limited to a value which is less than the clock pulse interval. A capacitor (22) is charged and discharged via a controlled switch (24). The output voltage is applied to a comparator (26) whose second input is fed from the output of the multiplexer (16) via a switch (46). This switch is controlled by a monostable (42) forming part of the limiting circuit and which is triggered after each clock pulse (A) and resets before the next clock pulse. The monostable is driven by another monostable (38) whose pulse sets the output bistable (44) of the modulator.