| 摘要 |
A counter stage includes a clocked transmission gate which, when turned on, couples the output of the stage back to its input. A resetting circuit is connected to the input of the stage for selectively clamping the input to a fixed voltage level representative of a logic one or a logic zero. The resetting circuit is enabled only when the clocked transmission gate is turned off, whereby no current can flow from, or to, the output via the resetting means. This enables high speed of reset since the input of the stage is then easily discharged (or charged) to the selected fixed level via the resetting circuit.
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