| 摘要 |
PROBLEM TO BE SOLVED: To output a reset signal by which a phase difference is returned to an initial state so as not to generate noise on a screen when the phase difference of a writing clock and a reading clock becomes large in a phase synchronizing circuit for inputting a serial digital video signal. SOLUTION: When the margin of the phase difference of a writing frequency- division clock 10 and a reading frequency-division clock 12 is nearly eliminated, a clock phase difference detection circuit 9 outputs a reset execution instruction 14. A reset signal generation circuit 19 outputs a reset signal 20 to an input side counter 6 according to a reset execution instruction 14 and sets the phase of a writing frequency division clock 10 to an initial state, while a reset timing signal 18 is outputted at a blanking period. |
