发明名称 PHASE SYNCHRONOUS CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL(phase-locked loop) which has a wide capture range and locks in quickly. SOLUTION: A PLL circuit is provided with a frequency control loop 5 and 7 to 10 in addition to a phase control loop 2 to 5 and alternately and repeatedly controls phase control and frequency control in each sector. Also, two systems of the PLL circuits are provided and timing control is performed so that one may be performed phase control when the other is performed frequency control and the output signal of a PLL circuit that is performed phase control is outputted. Then, a VCO(voltage controlled oscillator) quickly locks an input signal frequency in a frequency control period. And in the next phase control period, the VCO can be performed phase lock in a short time. Also, continuous clock signals can be outputted by using two systems of PLL circuits.
申请公布号 JPH10163865(A) 申请公布日期 1998.06.19
申请号 JP19960331650 申请日期 1996.11.27
申请人 SONY CORP 发明人 KANEKO SHINJI
分类号 H03L7/087;H03L7/113 主分类号 H03L7/087
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