发明名称 WIRING STRUCTURE AND FORMING METHOD OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce parasitic capacitance between conducting layer patterns by forming a plurality of the conducting layer patterns on a semiconductor substrate, forming insulating films on the semiconductor substrate and the conducting layer patterns, and forming at least one void in the insulating film between the conducting layer patterns. SOLUTION: A plurality of the conducting layer patterns 42 are arranged in parallel on a semiconductor substrate 40 via a first insulating film 41. Second insulating layers 43 are embedded in parts between the conducting layer patterns 42. The second insulating layers 43 form overhangs protruding from the upper edge parts of the conducting layer patterns 42 toward adjacent conducting layer patterns 42, and tip parts of the neighboring overhangs are brought almost into contact with each other. As a result, voids 44 are formed below the tip parts. Thereby a parasitic capacitance between conducting layer patterns 42 can be reduced, and operation characteristics of a device can be stabilized.
申请公布号 JPH11251428(A) 申请公布日期 1999.09.17
申请号 JP19980373267 申请日期 1998.12.28
申请人 LG SEMICON CO LTD 发明人 WAN CHORU SO
分类号 H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L21/768 主分类号 H01L21/768
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