| 摘要 |
<p>PURPOSE:To make synchronous leading-in slow and also to obtain a device of simple constitution whose circuit scale will not enlarge at the time of frame synchronization at a reception side for code transmission with frame-synchronous bits. CONSTITUTION:This device is equipped with frame detection circuit 24 which outputs a binary signal corresponding to a synchronization pattern by making a decision, bit by bit, on whether the frame synchronization pattern is included in sequence 16 of received codes, shift register 26 which has one-frame memory capacity, and coincidence detection circuit 28 which performs AND between outputs of circuit 24 and register 26. Further, this is provided with frame pulse generating circuit 13 which generates frame synchronizing pulses and synchronization protective circuit 11 which receives synchronizaing pulses of this circuit 13; in an asynchronization state, the output of circuit 28 is supplied as a reset signal to circuit 13 while the output of circuit 13 is supplied to both register 26 and circuit 11. In a synchronization state, on the other hand, the supply of the output of circuit 28 to circuit 13 is stopped and the same information as the output of circuit 24 is applied to circuit 11 by logical control circuit 65 provided.</p> |
