发明名称 MANUFACTURE OF SUBSTRATE PROVIDED WITH VIA CONNECTION
摘要 PROBLEM TO BE SOLVED: To provide the manufacture method of a substrate, whose thickness of a conductive region with which a via is filled is not restricted by the thickness of a patterned metallic layer and in which conduction layers which are mutually connected by the conductive via are installed on both faces. SOLUTION: A dielectric layer 100, where conduction layers 102 and 112 are deposited or stacked on one surface or both surfaces of a substrate, is used. Laser drill work is used for piercing a non-through via 104, which passes through a dielectric and stops at the boundary of the substrate and the conduction layer. For establishing electrical connection to the conduction layer, the via is filled with a conduction material 106 through an electrolytic plating process. A second conduction layer 108 is deposited o stacked on the other surface of the substrate.
申请公布号 JP2000286549(A) 申请公布日期 2000.10.13
申请号 JP20000065347 申请日期 2000.03.09
申请人 FUJITSU LTD 发明人 WILLIAM T CHOU;BEILIN SOLOMON I;MICHAEL G LEE;PETERS MICHAEL G;UEN-CHO VINCENT WANG
分类号 H05K3/40;H05K3/00;H05K3/42;H05K3/46;(IPC1-7):H05K3/40 主分类号 H05K3/40
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