| 摘要 |
A digital processor, digital memory or other digital information circuit is made compatible in a digital computer system which includes e.g., both 8 and 16 bit digital users within the system. The 16 bit system bus DAT is divided into a lower and an upper half 26a, 26b respectively with each half having separate lower and upper buffers 24a, 24b respectively. A swap byte buffer 28 (or, in an alternative position, 30), is provided for selectively coupling digital information on the upper half 22b of the local bus to the lower half 26a of the system bus, or to this via the lower buffer 24a. The upper, lower, and swap byte buffers are selectively enabled in response to a discrete command signal and to the least significant bit of an address. <IMAGE> |
