发明名称 MEMORY CIRCUIT OF STATIC OPERATION TYPE
摘要 PURPOSE:To establish the static type memory circuit less in element number and small in power consumption, by constituting the negative resistance element consisting of the back bias application to the PN junction formed at the first and second semiconductor areas, with the negative resistor. CONSTITUTION:The terminals 133,132,131 are picked up from the N and P type semiconductor area of the PN junction and the conductive elelctrode, respectively, to form the negative resistor through the application of the back bias voltage VD to the power supply terminal 170. The terminals 131 and 132 of the resistor L1 are connected to the memory terminal 140 together. The terminal 140 and the bit line 110 are connected via the source 113 of the enhancement type switching transistor TrT1 and the drain 112, and the gate 111 to the word line 120. The potential VA at the terminal 140 corresponds the potentials VL1 and VH1 corresponding to the operation stable points S1 and S2 of the resistor L1 to 0,1 of the memory information, to store them by charging up the capacitor C1. With this constitution, the number of elements is only L1,T1 and C1, the power consumption is less, to establish the static type memory suitable for circuit integration.
申请公布号 JPS54156439(A) 申请公布日期 1979.12.10
申请号 JP19780064287 申请日期 1978.05.31
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 UCHIDA YUKIMASA
分类号 G11C11/41;G11C11/412;H01L21/8244;H01L27/10;H01L27/11;H01L29/74 主分类号 G11C11/41
代理机构 代理人
主权项
地址