| 摘要 |
PURPOSE:To make it possible to determine the head-address information of the next page correctly in both page increase and decrease directions by using a full-adder. CONSTITUTION:The circuit consists of page addresses 1-0 and 5-0, intra-page addresses 1-1 and 5-5, full-adder 8, page increase and decrease direction indication FF9, inverter circuit group 10, one input terminal 11, the other input terminal 12, output terminal 13, and carry-in terminal 14. When the page update is carried out in the page increase direction, given logical page address 1 is supplied to terminal 11 of full-adder 8 to make all bits equivalent to address 1-0 ''0'' and then, bits complementary to ''2'' in terms of address 1-1 are supplied to terminal 12. As a result, logical address information 5 with address 5-0 represented by [3] on the decimal numeration system and address 5-1 by [0] is obtained, which is the head address of the next page. |
