| 摘要 |
Velocity error control apparatus for use in a video signal time base corrector of the type including a main memory having addressable storage locations for storing successive lines of video signals, write-in circuitry including a write-in clock signal generator synchronized with time base errors in the video signal for writing successive lines of video signals into addressed storage locations at a write-in clock signal rate, and read-out circuitry including a controllable read-out clock signal generator for reading out successive lines of video signals from addressed storage locations at a substantially constant read-out clock rate. The velocity error control apparatus includes a velocity error detector for detecting velocity errors in successive lines of the video signals which are written into the main memory. A velocity error store has a plurality of storage locations, each being operative to store a velocity error signal representing the velocity error of an associated line of video signals, and a velocity error read-out circuit reads out the velocity error signal from the velocity error store, which velocity error signal is associated with a line of video signals when the associated line of video signals is read out from the main memory. A modifying circuit modifies the read out velocity error signal as a function of at least one velocity error signal which is associated with at least one adjacent line of video signals. The modified velocity error signal is used to modulate the read-out clock signals so as to compensate for the velocity errors in successive lines of video signals. |
