发明名称 PHASE LOCKED CONTROLLER
摘要 A phase lock loop is illustrated which includes clamp means for controlling the rate of change of the output phase to no more than a preselected value. This feature has been found to be beneficial in certain applications such as temporary restraint of the dynamics of a phase lock loop of a data alignment unit of a communications system where downstream equipment cannot tolerate more than a predetermined phase change per unit time without losing synchronization.
申请公布号 JPS54154249(A) 申请公布日期 1979.12.05
申请号 JP19790030539 申请日期 1979.03.14
申请人 ROCKWELL INTERNATIONAL CORP 发明人 JIEIMUZU ROBAATO JIENKINSU
分类号 H03L7/08;H03L7/085;H04L7/00;H04L7/033 主分类号 H03L7/08
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