| 摘要 |
<p>A clock recovery circuit for use with a high-speed data signal having a low signal to noise ratio is disclosed. The circuit includes a first phase-locked loop circuit (104) operating in a fast acquisition mode for acquiring the clock from a data signal (D), a second phase locked loop circuit (102) for operating in a normal mode to recover the clock signal (Crec) in the digital data signal once the first phase locked loop circuit (104) has acquired the clock from the data signal, and a switch circuit (sw1, sw2, sw3) responsive to switch control signals for switching between the first phase locked loop circuit (104) and the second phase locked loop circuit (102) after the first phase locked loop circuit (104) has acquired the digital data signal.</p> |
