| 摘要 |
In a multiprocessor system comprising several processors (1 ,2, 3) interconnected, through a common bus (6), to a memory unit (4) including common resources, which can be used by the several processor apparatus for accessing the common resources which grant access to a common resource by a processor only if such resource is not used by another processor in the meantime. The busy or free status of each resource is indicated in each resource by a lock bit, which is stored in a predetermined memory position. Such bit is brought to a first logical level by a TEST & SET command issued by a processor which interrogates and accesses the resources and to a second logical level by a RESET TEST & SET command when the processor release the resource. To avoid that a processor interrogating certain resources with a TEST & SET command, and finding them already busy, goes on holding the common bus and stealing memory cycles with subsequent periodic requests, untill the resources are released, any RESET TEST & SET command is notified to the several processors and latched thereon. Each processor, which has detected busy resources, before trying to access them again, waits for the reception of a RESET TEST & SET signal. |
