发明名称 DECODER
摘要 <p>PURPOSE:To restore the smooth picture, by separating the delivered signal into the data signal of one-bit and into the phase signal of n-bit, and selecting and reproducing one of the video elements based on the phase information among the possible 2<n> sets of video elements. CONSTITUTION:The signal representing the phase information in 3-bit and the data 0 or 1 are fed from the terminal 11, and the phase information is fed to the selection circuit 16 to select the clock having the phase in correspondence, and the ouput h is given to the circuit 17 via the line 21. The phase set circuit 17 operates so that the first data signal i in video element is inverted with the clock h.</p>
申请公布号 JPS54153517(A) 申请公布日期 1979.12.03
申请号 JP19780062736 申请日期 1978.05.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OKANO HIROSUKE;TAKADA YUKIO;SAEKI HIROAKI
分类号 H04N19/00;G09G5/36;H04N1/40;H04N1/411;H04N7/12 主分类号 H04N19/00
代理机构 代理人
主权项
地址