发明名称 ALLOCATION CONTROL SYSTEM FOR TIMEEDIVISION MULTIPLE CIRCUIT
摘要 PURPOSE:To send out pieces of information sequentially according to idle states of time slots, and also on preferential basis by making a discrimination among time slots according to priority levels in a time-division multiple network system provided with time-division multiplexers. CONSTITUTION:Multiplexers 2-0 to 2-2 provided with channels 4 to 12 connected to time-division multiple circuits 21 to 26 and port adaptors 13 to 16 connected to terminals 17 to 20, thereby forming time-division multiple network 1 in which circuits 21 to 26 are linked by multiplexers 2-0 to 2-2. Then, channels 4 to 12 are provided with the sending address buffer part which controls time slots on circuits 21 to 26 against a transmission request. On the bais of the control of the buffer part, information is sent out via a free time slot among time slots corresponding to the transmission request, and a discrimination among time slots is made according to information priority levels, so that when a time slot low in priority level is idle, high-level information will be sent out.
申请公布号 JPS54152904(A) 申请公布日期 1979.12.01
申请号 JP19780062023 申请日期 1978.05.24
申请人 FUJITSU LTD 发明人 MATSUOKA KAZUO;FUJIMURA NORIAKI;SHIBATA TOMOHITO;HASHIMOTO SHIGERU;IHI TOSHIAKI
分类号 H04J3/00;H04J3/16;H04J3/24;H04L12/52;H04Q11/04 主分类号 H04J3/00
代理机构 代理人
主权项
地址