| 摘要 |
PURPOSE:To miniaturize a chip by making connection between transistors on p and n-type semiconductors of a complementary circuit via a connection hole extending to both semiconductors. CONSTITUTION:A poly Si layer (indicated by oblique broken lines) is formed spreading over both p-channel FET formation region 11 and n-channel FET formation region 14. For region 11, p-type poly Si is used and for region 14, n-type poly Si is used. Connection hole 20 is provided extending over both regions and both Si regions are connected together via metal. Consequently, troublbe such as pn junction between regions 11 and 14 is eliminated and no dead space is formed, so that the chip can be miniaturized. |
