| 摘要 |
A method and an apparatus for encoding and decoding a binary digital data signal is disclosed. An input signal that is to be encoded for transmission is shifted through a serial shift register with the bits in the stages of the shift register at each of the successive shift periods being used to define a binary coded addressable location in an associated memory. The memory has stored in each of its addressable locations a further binary code that when addressed by the shift register produces, as an output, a binary True or Complement signal which through a True/Complement generator couples the True or the Complement of the input signal to the transmission medium. The receiving end of the transmission medium has a similar arrangement of shift register, memory and True/Complement generator that decodes the received encoded transmitted signal.
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