| 摘要 |
PURPOSE:To reduce the chip occupied area of the element by using the load element giving termination to the digit line as the variable resistance means and securing a lower resistance value for the reading time than the writing time. CONSTITUTION:In the static memory cell array consisting of memory cells 11, 12, 21 and 22, digit lines D10, D11, D20 and D21 are terminated via MISFETQ100, Q101 and Q201 to be used as the load elements. And signal R is applied to each gate. Here, the level of signal R is set at a high and low levels to secure a small and large impedance for the terminal FET at the reading and writing time each. As a result, the level of the digit line features the same value as in the case of the O reading cycle before switching at the moment when the O writing cycle is switched to the 1 rading cycle, thus obtaining the readging time of about the same level regardless of the state before switching. Furthermore, the impedance of terminal FET is made large at the writing time, and thus the chip areas can be reduced for switching elements Q30, Q31, Q40, Q41, etc. |
