| 摘要 |
PURPOSE:To increase the access velocity to the memory from the high-speed bus by dividing the memory into units and also providing the data register plus the address register in which the controller to control the high-speed bus is formed in two steps. CONSTITUTION:In the memory control unit which controls the access to the memory from the high-speed bus, memory 1 and 2 are divided into plural units, and address register 11 and 13 plus data register 12 and 14 are provided to each of the divided units. And in case the writing request is given from high-speed bus H- BUS, the information is given to register 12 and 14 plus register 11 and 13 via address registers 15, 17 and 19 plus 16, 18 and 20 each which are provided in two steps as well as through bus A-BUS and D-BUS respectively. Thus, both bus A- BUS are used in time division. |
