发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To ensure the coexistence on the same chip for both the P-MOS and the bipolar transistor without impairing the high frequency characteristics of the N-MOS. CONSTITUTION:N<+>-layer 4a and 4 are formed on P-type substrate 1 with stacking of P-epitaxial layer 23 to form N<->-layer 24, 25 and 26 reaching the buried layer. Then a selective diffusion is given to layer 24 and 26 to form P-layers 27-29, and furthermore N-layers 30-32 are formed selectively to layer 27 and island region 23a. The insulator thin film is provided between layer 32-33 and 28-29 with installation of gate electrode 17 and 20, and at the same time the electrodes are provided to other layers with drilling of windows to the insulator film. In such structure, it is not necessary to form channel 35 of P-MOS in an independent way, thus the manufacturing process being reduced. And layer 23a of N-MOS features the N-type inversion on the surface of the N<->-epitaxial layer to be directly used as the depletion- type N-MOS, featuring the stable control of the threshold voltage because of the dependence only on the density of the epitaxial layer. Thus, the N-MOS excelling in the high frequency characteristics can be manufactured with a high controlability.
申请公布号 JPS54148388(A) 申请公布日期 1979.11.20
申请号 JP19780056775 申请日期 1978.05.12
申请人 NIPPON ELECTRIC CO 发明人 WATANABE HIDETAROU
分类号 H01L21/8249;H01L27/06 主分类号 H01L21/8249
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