| 摘要 |
<p>MODULAR SLOT INTERCHANGE DIGITAL EXCHANGE Up to k (e.g. 4) slot interchange memory/switch modules operate under common control to provide varied time interchange connective pairing associations between space divided telephone and data lines and time divided channels of digital trunks. A high scanning rate combined with dot-OR'ed (commoned) busing of addresses and outputs of all interchange modules permits in-service expansion of interchange switching capacity, from the capacity of 1 module to that of k modules, with minimal re-work of existing circuits and common control programs. The interchange slot locations of the aggregate array are thereby linkable in paired randomly ordered time interchange associations, over the entire addressing range of the aggregate. Additional interchange spaces are available in each switch module for interchanging activity bits in association with information traffic. These bits are useful for companding control, echo cancellation, TASI and network routing. Activity bits associated with input load to individual trunks are processed to form a TASI mask for out-of-band transmission over a channel of the respective trunk. Trunk channels are allotted to the traffic in accordance with respective bits of the mask. If the input load exceeds the capacity of a frame the mask is structured to effectively free out (and cancel) part of the traffic load. Traffic to be cancelled is selected in a predetermined order of priority favoring data over voice (talkspurt) activity and continuing talkspurt activity over initial talkspurt activity. The selection is complicated due to the short time available between the sensing of potential overload and the transmission of the TASI mask. Freezeout rates exceeding a predefined threshold are monitored and reported through the interruption facility of the common controls as an information parameter useful for high level network management. A network management system linked to a network of such exchanges may thereby reconfigure "route" tables governing slot interchange assignments to balance trunk loads throughout the network. The slot interchange timing cycle and addressing capability are designed to permit establishment of line-to-line "local" interchange connection associations as well as link-to-trunk "toll" associations. Trunk traffic is aggregated in large bit blocks per channel for communication efficiency(high ratio of traffic to link control information).</p> |
