发明名称 |
Loop system for data processors - reduces waiting time in on=line operation when one terminal is non-operational |
摘要 |
<p>The loop system is designed to reduce waiting time in the event of a data terminal being out of action. The system incorporates an interface which is placed between a modem and the data terminal. The interface has a data switch which is connected to a serial-parallel converter (37). The output is connected via an address encoder (39) to a microprocessor (40) acting as address detector and acknowledgement generator. When one terminal is out of service, the microprocessor calls up the previously stored acknowledgement signal from a memory (44) and sends it to the modem. The central computer instead of waiting, is instructed to switch to the next terminal in the series to be interrogated.</p> |
申请公布号 |
FR2423934(A1) |
申请公布日期 |
1979.11.16 |
申请号 |
FR19790010272 |
申请日期 |
1979.04.12 |
申请人 |
CEA ELEKTRONIK AUTOMATION GMBH |
发明人 |
ULRICH BOLLINGER |
分类号 |
H04L1/24;(IPC1-7):04L5/00 |
主分类号 |
H04L1/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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