| 摘要 |
PURPOSE:To enable to perform the signal error collect and double error detect effectively to failures of ROM package, by selecting and outputting 1 bit among a plurality of bit outputs of each ROM package. CONSTITUTION:The ROM packages 11 to qs are for output data storage, 11' to rs' are for check bit storage, and the ROM packages in one line are provided for the number equal to the sum of the number of bits q and the number of check bits r of one word length of the output data. When the address signal is given, with the decoder DEC, for example, the ROM packages 11 to q1 and 22' to R1' are enabled. Accordingly, the data in m-bit is read out and given to the selectors SEL1 to q, and 1' to r', where one bit among m-bit is selected and is inputted to the signal error correct SEC circuit and double error detect circuit SDC. The circuit SDC performs SEC and DEC to output the data in q-bit. |
