High electron mobility transistor and method of forming the same

摘要

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.

主权项

1. A high electron mobility transistor (HEMT) comprising:
a first III-V compound layer; a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition; a dielectric passivation layer disposed on the second III-V compound layer, an opening being through the dielectric passivation layer; a source feature and a drain feature disposed on the second III-V compound layer, and extending through the dielectric passivation layer; a gate electrode disposed over the second III-V compound layer between the source feature and the drain feature and disposed at least partially in the opening of the dielectric passivation layer; an oxygen containing region embedded at least in the second III-V compound layer under the gate electrode, the oxygen containing region being laterally defined by the opening of the dielectric passivation layer; and a gate dielectric layer under the gate electrode and on the oxygen containing region and wherein the gate dielectric layer is further along and contacting sidewalls of the opening of the dielectric passivation layer and over a top surface of the dielectric passivation layer, and further comprising a dielectric cap layer over a top surface of the gate electrode, along sidewalls of the gate electrode, and over and contacting the gate dielectric layer, and wherein the source feature and the drain feature further extend through each of the dielectric cap layer and the gate dielectric layer.