发明名称 Semiconductor packages and methods of forming the same
摘要 Disclosed are semiconductor packages and methods of forming the same. In the semiconductor packages and the methods, a package substrate includes a hole not overlapped with semiconductor chips. Thus, a molding layer may be formed without a void.
申请公布号 US9373574(B2) 申请公布日期 2016.06.21
申请号 US201313935456 申请日期 2013.07.03
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Jang Ae-nee;Kim Young Lyong;Jang Jaegwon
分类号 H01L23/13;H01L23/498;H01L21/56;H01L23/00;H01L25/065 主分类号 H01L23/13
代理机构 Renaissance IP Law Group LLP 代理人 Renaissance IP Law Group LLP
主权项 1. A semiconductor package, comprising: a package substrate including at least one hole; a first semiconductor chip mounted on the package substrate and not overlapped with the at least one hole; a second semiconductor chip mounted on the first semiconductor chip by a flip chip bonding method; and a molding layer on the package substrate, wherein the molding layer comprises: a first molding portion covering the second semiconductor chip, the first semiconductor chip and the package substrate and filling a space between the first and second semiconductor chips; and a second molding portion connected to the first molding portion through the at least one hole and disposed adjacent to a bottom surface of the package substrate, wherein the first semiconductor chip has substantially the same structure as that of the second semiconductor chip; and the first semiconductor chip and the second semiconductor chip are substantially symmetrical to each other with respect to a bump disposed therebetween; wherein the first semiconductor chip is connected with the package substrate by a bonding wire; wherein the first semiconductor chip includes a first bonding pad in contact with the bump and a second bonding pad to which the bonding wire is bonded; and wherein the second semiconductor chip includes a third bonding pad in contact with the bump and a fourth pad electrically insulated from the wire and the bump.
地址 KR