Fail=safe logic with AND=gate and memory - produces programmed signal whose delayed delay time is only shortened if component fails

摘要

The logic circuit produces a programmed signal with delayed decay time. It is designed so that if a component fails the delayed decay time is only shortened or disappears. A fail-safe AND-gate and a fail-safe memory are connected together such that the input of the AND-gate that receives the input signal is connected to one input of the memory. The output of the memory is fed back to that input of the AND-gate that receives the clock pulses. The AND-gate output is connected via a growth OR-gate to the growth input of the memory. Both the AND-gate and the memory have capacitors to maintain a time-limited control potential.