| 摘要 |
PURPOSE:To secure the optimum resistance value for the load of the memory cell with the memory unit in which the load resistance is connected in series to FET by forming the load resistance with the poly-crystal Si layer via the insulator film and then varying the resistance value according to the bias potential of the semiconductor region. CONSTITUTION:Thick SiO2 film 2 plus thin SiO2 film 3 enclosed by film 2 are coated on P-type Si substrate 1, and resist film mask 20 is formed on film 2. Then the N-type impurity ion is injected through film 3 exposed at the area where the resistance is to be formed later, and thus shallow N-type region 92c and 92d are formed within substrate 1. After this, poly-crystal Si layer 21 featuring the changing resistance is grown on the entire surface, and film 3e and poly-crystal Si layer 7 are made to remain at the center on region 92c through etching with film 3f and layer 7 left on the entire surface of region 92d. Then N<+>-type region 92a is formed by diffusion within region 92c exposing across film 3e, and layer 7 is covered with SiO2 film 22 and 23. And PSG film 10 is coated over the entire surface with wirings 12-14 formed at the fixed areas respectively. |
