Processor controlled memory refresh

摘要

In an electronic data processing system having a plurality of dynamic memory units associated therewith, the presently disclosed technique simultaneously refreshes a plurality of asynchronously operating memory units providing synchronous availability to the processor. The processor includes means for determining whether any of the memory units will be required by the processor within a time interval required to perform a refresh operation and, if not, then a "force refresh" signal is sent to the memory system to synchronously refresh all the memory units. Each of the dynamic memory units retains its internal refresh scheme to prevent loss of the stored information in the event that a force refresh signal is not received within the retention time of the dynamic memory unit.