| 摘要 |
A minicomputer comprises a microprogrammable central processing unit wherein micro-instruction execution speed is optimized through the use of variable micro-instruction timing logic and by grouping micro-instruction according to execution time. Furthermore, data paths are arranged so that micro-routines that implement more complex operations, i.e., memory reference instructions, follow the fastest route possible. When micro-instructions requiring longer data paths are programmed, the computer dynamically varies the length of the microcycle to be a function of both the type of micro-instruction to be executed and the state of the minicomputer when the micro-instruction is to be executed. A microprogrammable processor port is provided to allow coupling of external hardware, e.g., I/O devices, other processors, etc., directly to the microprogrammed control processor. This capability is in addition to the standard input/output system of the minicomputer, thereby providing an alternate interface path for devices requiring very fast transfer rates. These devices interfaced through the microprogrammable processor port are directly coupled to the internal data busses of the minicomputer and addressed under direct microprogram control as if they were internal processor registers. Block transfers of data are provided via this microprogrammable port to allow transfers of large blocks of data without dependence on the I/O system timing of the minicomputer. A remote program load feature is provided whereby an I/O device or data communications interface can initiate a bootstrap operation in a remote computer, i.e., the computer can be halted, a preselected ROM loader program is transfer into memory, all input/output instructions in the loader are automatically configured to the proper select code of the I/O device, and the computer is restarted at the proper loader program starting address.
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