| 摘要 |
A plurality of differential amplifier units are cascade connected into a plurality of stages. Odd numbered units except the last unit are double end units whereas even numbered units are single end units. Each unit comprises first and second transistors. The control electrode of at least one transistor of a succeeding unit is supplied with the output of a preceding unit. An input is applied to the control electrode of the first transistor of the first unit, through an external input terminal, and the control electrode of the second transistor of the first unit is grounded in the sense of alternating current through an external grounding terminal. The input terminal and the grounding terminal are interconnected through an impedance. The output of the last unit is fed back to the control electrodes of the second transistors of the odd numbered units.
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