Recognition of discrete frequencies - involves phase comparator whose output signal controls ratio of frequency divider

摘要

A phase synchronised loop is used. It contains a phase comparator, a constant frequency oscillator and a frequency divider with a variable division ratio controlled by the comparator output signal. The phase comparator analogue output signal is converted into a binary signal serving as the control signal for the variable frequency divider. Its keying ratio is proportional to the comparator analogue output signal. The phase comparator (1) receives an input from variable frequency divider (3) producing a signal (fFT) and the input (FE). Its output (UVergl) passes to a control circuit (R) connected to the frequency divider (3).