| 摘要 |
PURPOSE:To ensure the facilitated production of the parity bit and the parity check PC for the nonsynchronous input register by producing the expected parity. CONSTITUTION:In case the odd parity is adopted, FFO-FFn are all reset for register REG as the initial setting. Thus, output signals BO-Bn of REG are 0 with parity bit Bp turned to 1. Expected parity production circuit PG detects the variations for nonsynchronous set input signals STO-STn and reset signals RSO-RSn to deliver inversion signal rs, and turns signal rs to 1 only when detecting the variation of the odd bit. If signal ST1 turns to 1 after the initial setting, bit Bp becomes 0. The PC circuit performs PC with signals BO-Bn plus Bp. And only signal B1 is 1 and the bit of 1 features odd-number units and with Bp of 0. Thus, the odd parity becomes good with no error signal PE delivered. As a result, the PC can be facilitated. |
