发明名称 SEQUENTIAL CONTROLLER
摘要 PURPOSE:To enable easy monitoring of set points and present values of a timer and a counter by holding and displaying one or both of the present value and set point memorized in a memory when the element number of the timer or counter accords with the set point in a setter. CONSTITUTION:A decoder 25 generates an output when the instruction data are timer instruction and/or counter instruction. A comparator 28 generates an output when the input-output address fed to a register 22 accords with a set point in a setter 27. When the inouts to an AND gate G5 are equal to each other, the set points and present values of a timer and a counter are latched on registers 23 and 24, held over one scanning time, and displayed on displayers 31 and 32.
申请公布号 JPS54130777(A) 申请公布日期 1979.10.11
申请号 JP19780038687 申请日期 1978.03.31
申请人 发明人
分类号 G05B23/02;G05B15/02;G05B19/02;G05B19/05 主分类号 G05B23/02
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