发明名称 DATA ACCESS CONTROL SYSTEM
摘要 PURPOSE:To improve performance of a microprogram muPG control computer by attaining access to memory twice when the length of data of the memory to which access should be attained surpasses bounder 11. CONSTITUTION:In the muPG controller equipped with main memory MM from and to which data are read and written on a boundary unit, address information is set into memory address register MAR1 and the data length for access and information on the access direction are both set into length register L5 and the DR register respectively and transmitted to MM, thereby attaining the 1st access. At the same time, check circuit 3 makes a check on whether or not the length exceeds the boundary; when exceeding, an over-boundary flag is set to register 4, the remaining data length is calculated by adder 6, and the memory address and length are updated, thereby attaining the 2nd access. In this case, the lower bits of the memory address information are set into OPBS register 12 and memory data register 8 is shifted through shift control 7.
申请公布号 JPS54129934(A) 申请公布日期 1979.10.08
申请号 JP19780037919 申请日期 1978.03.31
申请人 FUJITSU LTD 发明人 TAKADA HIROSHI;KURIYAMA MASAHIRO
分类号 G06F9/34;G06F12/04 主分类号 G06F9/34
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