| 摘要 |
PURPOSE:To enable to pick up the output signal having no distortion, by connecting the element which can vary the AC voltage drop between the both terminals of the element giving the DC bias to the output stage. CONSTITUTION:The series connection circuit consisting of the semi-fixed resistor VR and the capacitor C1 is connected between the gates of N and P channel FET Q2, Q3 in complementary connection, and the resistor R2 is connected in parallel with it, and the resistor R1 is connected between the power supply +Vcc and the gate if Q2. Since the mutual conductance of Q2 is greater than that of Q3, Q2 can easily be operated if the drive voltage en of Q2 is smaller than that en of Q3. That is, taking as en<ep, Q2 and Q3 can be operated in good balance. When VR is adjusted so that the resistance value is greater, en<ep, AC balance can be taken for the output signal. In comparison with shortening VR in AC, for the harmonics at fundamental frequency 1 kHz, the secondary harmonics can be reduced by about 10 dB and the fourth harmonics by about 15 dB, and the sixth or more harmonics can be zeroed. |
