发明名称 |
SEMICONDUCTOR MEMORY |
摘要 |
Each memory cell of an x-y addressable semiconductor memory includes a charge storage element serially connected with an I-O (bit) line through a pair of CCD-type transfer gates. One gate is responsive to x-addressing and the other gate to y-addressing. When an x-y address is selected only the charge storage element of the one selected memory cell communicates with the bit line. |
申请公布号 |
JPS54129842(A) |
申请公布日期 |
1979.10.08 |
申请号 |
JP19790033780 |
申请日期 |
1979.03.22 |
申请人 |
HEWLETT PACKARD YOKOGAWA |
发明人 |
JIEEMUSU AARU IITON JIYUNIA;CHIYAARUZU JII SODEINI;ROORENSU JII UOOKAA |
分类号 |
G11C11/401;G11C11/35;H01L21/8242;H01L23/535;H01L27/10;H01L27/108 |
主分类号 |
G11C11/401 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|