发明名称 PHASE LOCK LOOP CIRCUIT
摘要 PURPOSE:To focus a phase difference between reference input signal FS and voltage control oscillator VCO to zero, by equipping a PLL circuit with a method of controlling the phase of VCO by the output signal of a phase comparator circuit. CONSTITUTION:Reference input signal FS2(10) and output signal 11 of VCO14 are both inputted to phase comparator 3 and then a phase difference between both the signals is detected by circuit 3 to generate phase-difference pulse 12, which is supplied to charge pump circuit 4. circuit 4 gnerates a discharge pulse when the VCO signal leads the FS signal or a discharge pulse when the VCO signal lags the FS signal. Either charge or discharge pulse is applied to integrating circuit 5, whose output voltage is then applied to the control voltage terminal of VCO14, so that the oscillation frequency will vary with the phase. In this case, control voltage 13 from circuit 5 to VCO14 focuses to constant value VG through the phase control by applying the phase control signal from the output of circuit 3 to terminal 15 of VCO14, so that the phase difference between signal FS and the output signal of VCO will focus to zero.
申请公布号 JPS54129959(A) 申请公布日期 1979.10.08
申请号 JP19780037634 申请日期 1978.03.31
申请人 CITIZEN WATCH CO LTD 发明人 FUJITA HIROO;TSUZUKI AKIRA
分类号 H03L7/081;H03L7/08 主分类号 H03L7/081
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