发明名称 FREQUENCY DIVIDER
摘要 PURPOSE:To obtain high resolution while maintaining a high reference frequency by changing over outputs of respective stages by using a ring counter for a pre-scaler part in a PLL circuit. CONSTITUTION:For example, the division ratio of variable divider is set to three. The output of voltage control oscillator 1 is divided by pre-scaler 2' of two in division ratio and inputted to four-stage ring ocunter 7. Signal selector circuit 8 selects signal Q1 of counter 7 and transmits it to divider 3. Divider 3 outputs three pulses Q1 and this output signal is processed by selection control circuit 9 to switch the input of circuit 8 to Q2. By three pulses Q2, Q3 is selected in the same way, and at every time of the execution of divider 3, the output of counter 7 is switched in the order of Q1, Q2, Q3, Q4, Q1... Therefore, the output signal of circuit is shifted by a quarter period at each joint to allow divider 3 to operate as if having a 3+1/4 division ratio. Consequently, high resolution can be obtained without requiring a high-speed circuit while maintaining a high reference frequency.
申请公布号 JPS54129960(A) 申请公布日期 1979.10.08
申请号 JP19780038365 申请日期 1978.03.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NEZU SHIYUNICHI;KANE JIYOUJI;OKAMOTO MICHIO
分类号 H03K23/40;H03J5/00;H03K23/54;H03K23/58;H03K23/64;H03K23/66;H04B1/04;H04B1/26 主分类号 H03K23/40
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