| 摘要 |
PURPOSE:To enable to prevent mis-detection, by greatly reducing (about 1/3) the hardware, through the exclusive logical sum for each latch to detect the error of operation for the data transfer control system. CONSTITUTION:In the input and output selection latches 8, 10 and the mark latches 14, 15, when one is inverted, then another corresponding to it is also inverted. The data transfer control system error check circuit CKT consists of the exclusive logical sum circuit 16 and the error latch 17. When the initial value of the latches 8, 10, 14, 15 is taken as ''0'', the value of the exclusive logical sum 16 of each latch 8, 10, 14, 15 is always ''0'', as far as the system normally operates, excepting transient phenomenon, and accordingly, the latch 17 is ''0''. Next, if there is wrong sequence to the latches 8, 10, 14, 15, the output of the circuit 16 is ''1'' and accordingly, the latch 17 is ''1''. The error of the system is informed through the error line 25. |
