| 摘要 |
PURPOSE:To reduce the number of both the information line and the input/output terminal by supplying and delivering the address information and the write/read information in the time-division system. CONSTITUTION:Multiplexer 2 is provided at the address data input/output part of random access memory (RAM) 1, the the address signal line and the data signal line are used in common inside RAM1. Multiplexer 2 consists of transmission gate MISFET (Q1-Q5) which uses the common information line or input/output terminal in time division. In other words, the allotment in terms of time is given to the address and the data via control signal D/A which prescribes the input/output control for the address and the data, and the distinction is given between writing data (din) and reading data (dout) by the write/read order (r/w). |
