| 摘要 |
PURPOSE:To control transmission-reception timing by directly connecting each other devices different in data processing rate and by sending out a signal level which expresses the incapability of transmission and reception of next data after data transfer so that mutual communication will be done only via communication lines of data lines. CONSTITUTION:When transmission circuit 1 is ready for reception, a signal is received which is shown by B, a low-level signal following the oblique-line part is stored as a timing signal in converter circuit 11, and after the transfer, a reception-flag signal is outputted as a low-level signal, so that reception-end detection circuit 14 will be reset. Then, the reception flag allows the CPU to start repetitive operation. Once the data reception ends, no reception flag is outputted from circuit 11, the reset operation of circuit 14 is stopped, and a counting shift is made character by character as much as the fixed number of digits. As a result, dissidence gate 24 becomes high in level to output a signal shown by A and FF15 generates a high level output to allow circuit 11 to receive a high input, so that data will never be fetched. |
