发明名称 ERROR CORRECTION SYSTEM
摘要 PURPOSE:To enhance the correcting capacity for the continuos burst error up to the m-bit via the grown polynomial up to the m-ordered place regardless of the position of the information bit. CONSTITUTION:Switch 3 has a contact to contact (a) until the full bits 1-K are supplied for information bit input e1 and then connected to shift register 5. When switch 3 is changed to contact (b), the contact to (b) is kept up to the full bits k + 1-k + m of parity bit C2 which are the output of register 5 for input e1. And gate 1 opens for 1-k and closes for k + 1-k + m. While switch 4 has first a contact to (a) for input e1 and 1-k + m bits and then connected to register 6, and gate 2 opens for 1-k + m bits and closes for k + m + 1-k + 2m bits respectively. Thus, the continuous burst error up to the m-bit can be corrected via the grown polynomial up to the m-th order at any optional position of the information bit, enhancing the error correcting capacity.
申请公布号 JPS54125901(A) 申请公布日期 1979.09.29
申请号 JP19780032955 申请日期 1978.03.24
申请人 SONY CORP 发明人 SHIROTA NORIHISA
分类号 G06F11/10;H03M13/00;H03M13/17 主分类号 G06F11/10
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