| 摘要 |
<p>PURPOSE:To make it possible to use a good-transmission efficiency continuous synchronous system by detecting the polarity of receiving data and generating clocks which performs correctly sampling of receiving data on a basis of this detected polarity. CONSTITUTION:When the polarity of receiving data input 1 is changed, counter 10 is cleared forcedly, and output 13 becomes ''1'' for the purpose of setting forcedly flip-flop 12 which generates clocks for performing correctly sampling of receiving data. After that, output 13 of flip-flop 12 is changed from ''1'' to ''0'' at the logical center of receiving bits. Further, if receiving data bits have the same polarity, output 13 is changed from ''0'' to ''1'' at the boundary point of logical data bits. As a result, when receiving data input 1 is subjected to sampling at the trailing edge of output 13 of flip-flop 12, receiving data can be received correctly.</p> |
