| 摘要 |
<p>PURPOSE:To enable to most efficiently use the speed performance and to simplify the timing of the memory unit, by outputting the memory operation end signal and enabling easily to discriminate the end of the memory operation of the memory element from external easily. CONSTITUTION:The memory operation end output signal generating circuit 27 is provided. The circuit 27 is controlled with the internal control signal and the internal timing generating circuit 8, and the memory operation end output signals EO1...EOi...EOs are outputted at the time point of each memory operation end for the memory element. The address signals A1...Ai...An in n-bits enter the address signal input circuit 1, are decoded 2 and given to the memory cell arrangement 3, and the write-in data signals DI1...DIi...DIm in m-bit are written in the arrangement 3 via the readout and write-in data selection circuit 4 and the write-in data input circuit 5, and the memory information is read out to the readout data output circuit 7 via the circuit 4.</p> |
