发明名称 MEMORY ADDRESS CONTROL UNIT FOR DATA PROCESSOR
摘要 PURPOSE:To make easy the transition for the mode between the byte mode and word mode on CPU at ON-line state, by providing the shift unit etc. which convert the byte address into word address. CONSTITUTION:When the CPU 2 is of byte mode, the status FF3 is set to ''1'', and when the byte address 12(1100) address A in the main memory unit 1 constituted in word unit is called out, since FF3 is ''1'', the shift unit 4 has right 1 bit shift function, and the byte address 12(1100) address is converted into the word address 6(110) address and set to the memory address register 5. On the other hand, ''0'' shifted out from the unit 4 is stored in FF6 and gives 1 byte shift function to the byte shift unit 7. Thus, the content of the word address 6 read out from the unit 1 at the word address 6(110) of the register 5 is shifted right by one byte at the unit 7, and it is set to the memory read register 8.
申请公布号 JPS54123838(A) 申请公布日期 1979.09.26
申请号 JP19780031329 申请日期 1978.03.17
申请人 NIPPON ELECTRIC CO 发明人 TAZAKI MAKOTO
分类号 G06F12/04;G06F9/34 主分类号 G06F12/04
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