发明名称 |
ARRANGEMENT FOR THE GENERATION OF PULSE TRAINS FOR CHARGE-COUPLED CIRCUITS |
摘要 |
<p>An arrangement for generating pulse trains for charge-coupled circuits employs a plurality of series-connected master-slave JK flip-flop circuits in which a Q output of a flip-flop circuit is connected to a J input of the following flip-flop circuit and in which a terminal for obtaining the generated timing pulses is provided at each Q output of a flip-flop circuit. A pulse train input for providing timing pulses to the flip-flop circuits and for each flip-flop circuit an NAND gate is provided whose output is connected to the clear input of the flip-flop circuit. One input of the NAND gate is connected to the timing pulse input line and another input is connected to a Q output of the following flip-flop circuit, except for the last flip-flop circuit in which the other input of the NAND gate associated therewith is connected to the Q output of the first flip-flop circuit. The K inputs of the flip-flop circuits are connected to a fixed potential, preferably a common connection to ground, and the individual flip-flop circuits may be additionally set by way of the clear inputs. In one embodiment the arrangement is constructed for two-phase operation and in another embodiment the arrangement is constructed for three-phase operation.</p> |
申请公布号 |
CA1063188(A) |
申请公布日期 |
1979.09.25 |
申请号 |
CA19750217864 |
申请日期 |
1975.01.14 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
PFLEIDERER, HANS-JOERG;KNAUER, KARL |
分类号 |
G11C27/04;G06F1/04;H03K3/037;H03K5/15;H03K5/151;H03K23/80;(IPC1-7):03K3/286 |
主分类号 |
G11C27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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