| 摘要 |
A carrier correction circuit accepts a serial digital data input stream having an underlying carrier frequency associated with it and generates a corrected carrier signal synchronized with the underlying carrier frequency. The input stream may, for example, be a serial output of an analog-to-digital converter having a differential phase shift keyed analog signal applied to its analog input, the underlying carrier frequency being the carrier frequency of the DPSK signal. The carrier correction circuit includes a phase detector which receives the serial digital data input stream and two representations of the recovered carrier which are shifted in phase from each other by 90 DEG . Each of these representations of the recovered carrier is mixed with the serial digital data input stream by means of first and second mixer circuits, and the results are loaded into first and second serial accumulators, which accumulate, respectively, the average products of the two mixer circuits over a certain time period. A magnitude comparator periodically generates an error signal by comparing the magnitudes of the first and second serial accumulators. The carrier correction circuit includes a carrier correction filter which includes an up/down counter which counts up each time the error signal is a "1" and counts down each time it is a "0". The contents of the up-down counter are averaged to generate a number of correction pulses. A digital controlled oscillator accepts a sign bit and the correction pulses from the carrier correction filter in order to advance or retard the recovered carrier signal to synchronize it with the underlying carrier frequency.
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