发明名称 PHASE LOCKING LOOP WITH GRADED BAND WIDTH
摘要 PURPOSE: To prevent any confusion due to a noise generated at the terminal of a pre-amble, and to stabilize a loop itself in a short time by providing a loop controlling means connected with a signal generating means for generating a response control signal for exponential functionally decreasing an amplitude, which adjusts the response time of a phase lock loop according to the amplitude of the response control signal. CONSTITUTION: This device is provided with a signal generating means 11 which starts the exponential functional decrease of an amplitude in a time when the phase lock loop 10 receives a preamble part 34, and generates a response control signal for exponential functionally decreasing the amplitude at least in a time when the phase lock loop 10 receives a data part 36. Also, this device is provided with a loop controlling means connected with the phase lock loop 10 and the signal generating means 11, which adjusts the response time of the phase lock loop 10 according to the amplitude of the response control signal. Thus, a band width can be loosely decreased so that sensitivity to a lock complementing time and a noise can be reduced, and also the loop can be stabilized so that a time for attaining phase lock can be shortened.
申请公布号 JPH0221738(A) 申请公布日期 1990.01.24
申请号 JP19890120240 申请日期 1989.05.12
申请人 DIGITAL EQUIP CORP <DEC> 发明人 MAIKERU DEII RAISU
分类号 G11B20/14;H03L7/089;H03L7/107;H04L7/033 主分类号 G11B20/14
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